As shown in FIG. 1, in the design for a Gate On Array (GOA) of a Thin Film Transistor-liquid Crystal Display (TFT-LCD) in the prior art, the time for charging a pull-down node PD in a pull-down holding phase T4 is a 50% time, i.e. a time period in which a first clock signal CLKB has a high level. In the other half of time, i.e. a time period in which the CLKB has a low level, since a pull-down control node PD_CN cannot be turned off well, the potential of the pull-down node PD is pulled down with a second clock signal CLK, and noises of a pull-up node PU and a gate drive signal are large (in FIG. 1, Input indicates an input signal). That is to say, during the pull-down holding phase T4, when the first clock signal CLKB has a high level, the potential of the pull-down control node PD_CN can remain at a high level, so that the pull-down node PD switches to the first clock signal CLKB, and the potential of the pull-down node PD also becomes a high level. When the first clock signal CLKB has a low level, the potential of the pull-down control node PD_CN still remains at a high level, so that the potential of the pull-down node PD is pulled down, which might cause erroneous output at a gate drive signal output terminal.